The invention is concerned with the structure of a time division speech path switch which is used in a time division exchange system. (It will be called "C switch" in the description which follows.) Due to its facilities of both highway switching and time switching, any one of nk number of speech paths provided by k number of input highways, each having n number of multiplexing speech paths, can be connected without blocking to any one of nk number of speech paths included in k output highways, each having n number of multiplexing speech paths, in an arbitrary combination.
The structure of a C switch shown in FIG. 1 has been well known. In FIG. 1, the numeral 1 stands for a speech path memory, 2 stands for a holding memory. Each of the memories has a capacity of nk words for storing nk speech paths. A counter denoted by 3 is able to count from 0 to nk-1 and circulates with a clock whose period is 1/nk. (The frame period of time division multiplexing is chosen as a unit time.) A multiplexer circuit, denoted by 4, multiplexes the speech paths provided k input highways 6-1, 6-2, --- 6-k, onto a single input secondary high way denoted by 8. A de-multiplexer circuit 5 distributes the speech path provided by a single output secondary highway, denoted by 9, to k output highways 7-1, 7-2, --- 7-k. Counter 3 is synchronously operated with the multiple frame frequency of the input secondary highway 8. That is, when a signal of i'th speech path is coming into input secondary highway 8, counter 3 indicates i. with this as an address, the signal is written into a word of speech path memory 1 whose address is given by i. At the same time, a word, whose address is i, of holding memory 2 is read out and the content j is obtained. Then, a word with address j of speech path memory 1 is read out, and the read out information is sent out on the output secondary highway 9 as a signal in its i'th speech path. Meanwhile, a word with address j of holding memory 2 contains i (not shown in FIG. 1). When counter 3 indicates j, in the same way as explained above, a signal of j'th speech path of input secondary highway 8 is written into a word with address j of speech path memory 1, and the content stored in a word with address i of speech path memory 1 is read out and sent to output secondary highway 9 as a signal in its j'th speech path. In this way, signals are exchanged between input secondary highway 8 and output secondary highway 9 concerning their i'th and j'th speech paths. There is a one-to-one correspondence between the speech paths of input secondary highway 8 and those of input highways 6-1, 6-2, --- 6-k. The same is true also between the speech paths of output secondary highway 9 and those of output highways 7-1, 7-2, --- 7-k. The fact that any two speech paths can be exchanged between input secondary highway 8 and output secondary highway 9 means that any exchange can be realized between speech paths of all the input highways and those of all the output highways.
The well known C switch structure described above, however, has a drawback that it requires very high speed memory circuitry for both speech path memory 1 and holding memory 2. That is, as is obvious from the above explanation, speech path memory 1 must be accessed 2nk times for read-in and read-out during one frame period of time division multiplexing (for example, 125 .mu.s. in a PCM system) and holding memory 2 must be accessed nk times per frame period for read-out. This means the maximum speed of a memory element determines the capacity (=number of speech paths, i.e., nk) of a C switch of this type. In other work, the capacity of a C switch is limited by the operational speed of a memory.